A robust multi-bit soft-error immune SRAM cell for low-power applications

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage ( V DD ). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground ( V GND ) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at V DD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit.