Hardware And Software Implementation Of A Hardware Efficient Beamformer For Underwater Acoustic Communications

The operation of a hardware-efficient beamformer based on the 320C25 DSP chip is described in some detail; showing how considerable savings may be achieved by splitting the beamformer array into a number of smaller sub-arrays whose signals are processed by partial beamformers. Detail of the hardware design and operation is provided together with how charts for the software operation.