Top: An Algorithm For Three-Level Combinational Logic Optimisation

E. Dubrova,P. Ellervee,D. M. Miller,J. C. Muzio,A. J. Sullivan

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS（2004）

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摘要

Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type g(1degrees)g(2), where g(1) and g(2) are sum-of-products expressions and '(degrees)' is a binary operation. For the first time, to the authors' knowledge, this problem is addressed for an arbitrary operation '(degrees)', although several algorithms for specified cases of '(degrees)' have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser.

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关键词

circuit optimisation,combinational circuits,logic design,programmable logic devices,TOP,area reduction,binary operation,heuristic algorithm,multilevel implementations,product-terms expression,sum-of-products expressions,three-level combinational logic optimisation,three-level logic expression,two-level AND-OR minimizer,two-level implementations,

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