A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications

ISSCC（2010）

引用 15|浏览4

暂无评分

摘要

A 2 Ã 25 Gb/s deserializer for 100 Gb/s Ethernet is implemented in 65 nm CMOS technology. Employing regulated limiting amplifiers, full-rate CDRs, a built-in clock generator, and a 2:5 DMUX, this two-channel prototype achieves BER < 10-12 with 20 mVpp input sensitivity while consuming a total power of 510 mW.

查看译文

关键词

cmos integrated circuits,ethernet,power 510 mw,size 65 nm,amplifiers,voltage 20 mv,ber,demultiplexing,full-rate cdr,cmos technology,deserializer,bit rate 100 gbit/s,error statistics,local area networks,amplifier,built-in clock generator,clock and data recovery circuits,dmux,generators,synchronization,bit error rate,jitter

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要