Thin film embedded memory solutions

CMOS evolution at Moore’s law speed modulated by market demand is facing extrinsic and intrinsic limitations. Main extrinsic drawback is process variability affecting yield production. Solutions to address this point are focused on design and integration at dice level. Intrinsic limitations are usually summarized through the term Short Channel Effects, SCE. To overcome parasitic SCE, device engineers consider building aggressively shrink CMOS transistors on thin silicon film. These devices, allow a better electrostatic potential control.