Scalable cores in chip multiprocessors

Chip design is at an inflection point. It is now clear that chip multiprocessors (CMPs) will dominate product offerings for the forseeable future. Such designs integrate many processing cores onto a single chip. However, debate remains about the relative merits of explicit software threading necesary to use these designs. At the same time, the pursuit of improved performance for single threads must continue, as legacy applications and hard-to-parallelize codes will remain important.These concerns lead computer architects to a quandary with each new design. Too much focus on per-core performance will fail to encourage software (and software developers) to migrate programs toward explicit concurrency; too little focus on cores will hurt performance of vital existing applications. Furthermore, because future chips will be constrained by power, it may not be possible to deploy both aggressive cores and many hardware threads in the same chip. To address the need for chips delivering both high single-thread performance and many hardware threads, this thesis evaluates Scalable Cores in Chip Multiprocessors: CMPs equipped with cores that deliver high-performance (at high per-core power) when the situation merits, but can also operate at lower-power modes, to enable concurrent execution of many threads. Toward this vision, I make several contributions. First, I discuss a method for representing inter-instruction dependences, leading to more-efficient individual core designs. Next, I develop a new scalable core design, Forwardflow. Third, I evaluate policies by which to use Forwardflow cores in a scalable CMP. And lastly, I outline methods by which future researchers can pursue the performance characteristics of scalable cores without extensive simulation, paving the way for evaluation of system-level considerations.