Exploration of the Scaling Limits of 3D Integration

Three dimensional (3D) wafer bonding is an emerging technology that may be used to increase transistor densities by stacking devices over devices. The alignment of the wafers and the devices on them is a function of the mechanical capability of the wafer to wafer alignment tool and the thermal conditions of each wafer when bonded. However, as bonded wafers are thinned to 1% or less of their starting thickness the processes of bonding and thinning as well as previous process history affect wafer planarity and silicon stress. The drive to vertically interconnect circuit blocks at the sub-micron scale requires a high density of vertical interconnects and thinning a wafer to less than 5 μm enables through wafer via processing at a scale found in the first layers of the interconnect stack. In this paper the measurement of wafer to wafer alignment was done by comparing a metal pattern on a face down bonded silicon on insulator (SOI) wafer to a complementary metal pattern on the bulk wafer to which it was bonded. The effect of aggressive thinning is evaluated using thinned back to face bonded SOI wafers with functional devices and face down bonded non-patterned SOI wafers thinned after bonding. The face up bonded SOI wafers with functional devices were temporarily bonded face down to a Si-wafer I, thinned to the buried oxide (BOX), face up bonded with benzocyclobutene (BCB) on a Si-wafer II, followed by release of the temporary bond and electrical test. Raman and XRD stress measurements of the non-patterned SOI wafer silicon 70 nm and 110 nm thick SOI Si were taken before and after thinning, and the radius of curvature of the SOI wafers and the bulk wafer substrates was monitored. Thermo-mechanical models of SOI Si stress and bonded wafer curvature are compared to the measured results.