Predicting memcached throughput using simulation and modeling

The current work introduces a method for predicting Memcached throughput on single-core and multi-core processors. The method is based on traces collected from a full system simulator running Memcached. A series of microarchitectural simulators consume these traces and the results are used to produce a CPI model composed of a baseline issue rate, cache miss rates, and branch misprediction rate. Simple queuing models are used to produce throughput predictions with accuracy in the range of 8% to 17%.