The new 3-stage, low dissipation digital filter of the ALMA Correlator

Ab st ra c t - The main goal of this study is to reduce the powe r dissipation of the 2-stage digital filter used in the ALMA Correlator system. This has been achieved by optimizing the number of FPGA logic elements used for the filter implementation. We have investigated the implementation of various structures based on the Cascaded Integrator Comb (CIC) filter in order to replace th e present first filter stage, a 32-time demultiplex ed input decimation filter. We conclude that a CIC filter ca scaded with a quarter-band filter significantly imp roves the overall power dissipation and thus the FPGA thermal behaviour and reliability. This new design results in a significant improvement (nearly 25%) in the dissipa tion of each one of the ALMA filter cards .