Calibration-free 14b 70MS/s 0.13 [micro sign]m CMOS pipeline A/D converters based on high-matching 3D symmetric capacitors
Electronics Letters(2007)
摘要
A 14b 70MS/s pipeline A/D converter (ADC) in a 0.13 mum CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a die area of 3.3 mm2 shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB, respectively, at 14b
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关键词
analogue-digital conversion,capacitors,CMOS integrated circuits
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