A Low Jitter Clock And Data Recovery With A Single Edge Sensing Bang-Bang Pd

This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13 mu m CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17 ps on 2(5)-1 PRBS input pattern compared to 26 ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3 mW with the proposed BBPD.