Fast Test Simulation via Distributed Computing

Abstract Parallel processing techniques have been applied to logic simulation in the past with limited success. An aspect of this problem,that has received little research attention is the impact on performance,of application-specic simulation of test sequences. We approach the problem from this angle and identify an important practical application, simulation of manufacturing test patterns for ICs, which can be successfully parallelized. This is due to the high and balanced circuit activity that is typical of manufacturing tests. To exploit these characteristics, we develop several new techniques to reduce communication overhead and balance workload. We also describe a circuit partitioning methodology,based on these techniques, and evaluate the impact of hypergraph partitioning algorithms. Our empirical results show that the proposed approach can signicantly accelerate parallel simulation of manufacturing tests.