Precursor ISI Reduction in High-Speed I/O
2007 IEEE Symposium on VLSI Circuits(2007)
摘要
To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.
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关键词
decision-feedback equalization,inter-symbol interference,transmitter equalization,equalization adaptation,clock-data recovery,bit-error-rate,BER,backplane channels,transceiver architecture
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