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基于VHDL卷积交织器的设计与实现

Zhang Zirui,Sun Minhua

Natural Science Journal of Harbin Normal University（2010）

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Abstract
研究交织的原理,提出了一种VHDL来实现DOCSIS标准中的卷积交织器的方案,并且在ModelSim SE6.1d环境下进行功能仿真,该方法具有实现简单和占用资源少等优点.
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Key words
Interleaver,Dual-port RAM,DOCSIS
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