High temperature processing of poly-SiC substrates from the vapor phase for wafer-bonding

The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC substrate to obtain a “quasi-wafer” requires high quality polycrystalline substrates with controlled bulk properties (thermal conductivity, electrical resistivity) as well as with very low surface roughness (RMS<5 nm) and bowing (<10 μm). Currently, available polycrystalline SiC wafers are processed by sintering or by Chemical Vapor Deposition (CVD). Sintered ceramic wafers are very heterogeneous (mixture of 3C, 6H, 4H and silicon), while CVD ones are of better quality (homogeneous and textured 3C). The aim of this paper is to investigate the fabrication and the properties (bulk and surface) of SiC substrates with large (0.1 to a few mm) grains. To meet these requirements, two high temperature processes (around 2000 °C) for single crystal growth were used: Physical Vapor Transport (PVT) and the recently developed CVD Feed Physical Vapor Transport (CF-PVT). Structural investigations performed on large grain wafers sliced and polished from the grown ingots showed an important influence of the initial seed on the grain size, polytype and crystallographic texture. Chemical and Mechanical Polishing (CMP) of such structures was studied and optimized to obtain low surface roughness. The intra-grain roughness is very low (RMS<0.5 nm) but a few nanometer of height steps were observed between grains. The relations between bulk properties, surface functionalization and process conditions are discussed. This first seeding step with commercial substrates is necessary for the creation of original substrates which can be used for the fabrication of new substrates.