Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.