An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages
ISCAS（2010）
摘要
An 8-bit, 3-stage asynchronous gated ring oscillator (GRO) time-to-digital converter (TDC) is presented. It employs asynchronous techniques to achieve minimum GRO stages. This lead to about 40% to 70% gate count reduction compared to synchronous GRO-TDC. Count-missing, glitch, and unnecessary addition are eliminated. The uncorrupted noise shaping characteristic is obtained. The chip is implemented in a 0.18 μm CMOS technology. It occupies small area (140μm×310μm) and consumes low power (4mW to 13mW).
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关键词
synchronous gro-tdc,asynchronous techniques,analogue-digital conversion,time-to-digital converter,gate count reduction,cmos technology,size 0.18 mum,uncorrupted noise shaping characteristic,asynchronous circuits,oscillators,area efficient asynchronous gated ring oscillator tdc,minimum gro stages,adders,chip,radiation detectors,registers,ring oscillator,noise,time to digital converter,logic gates,noise shaping
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