Electrical modelling of lossy on-chip multilevel interconnecting lines
EURO-DAC '91 Proceedings of the conference on European design automation（1991）
摘要
A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analysis of coupled line systems with linear or nonlinear/time varying terminators, as well as for the study of the pulse propagation characteristics in high-speed ICs. Numerical results are presented for 3-D parallel and galvanically separated crossed planar lines.
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关键词
line system,lossy 3-d multilevel interconnection,3-d parallel,spice-like cad program,on-chip multilevel interconnecting line,line model,planar line,so-called method,electrical modelling,interconnection line constant,method of moments,packaging,solid modeling,vlsi,dielectrics,transmission line theory,very large scale integration,geometry,chip,voltage
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