Design Of A Digital Ip For 3d-Ic Die-To-Die Clock Synchronization

Mehdi Sadi,Sukeshwar Kannan,Luke England,Mark Tehranipoor

2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)（2017）

引用 30|浏览23

暂无评分

摘要

In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented. The proposed design offers notable benefits over the conventional dual DLL based architectures for 3D IC clock synchronization. Simulation results of the IP are presented with GLOBALFOUNDRIES 14nm finFET library, and Through-Silicon Via (TSV) technology.

查看译文

关键词

digital IP design,3D-IC die-to-die clock synchronization,DLL,GLOBALFOUNDRIES finFET library,through-silicon via technology,TSV technology,size 14 nm

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要