A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS
ISSCC(2013)
摘要
In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.
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关键词
cmos integrated circuits,digitally modulated wlan transmitter,radio transmitters,mobile device,wi-fi transmitter,dynamic load modulation,size 65 nm,dc-dc power convertors,ofdm modulation,integrated phase path,integrated cmos pa,frequency 2 ghz to 5 ghz,pa supply,peak-to-average-power-ratio,close-in spectral performance,on-chip matching network,wireless lan,papr,battery life,dc-dc converter
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