A digital TDC with a reduced number of delay line cells

In nuclear physics experiments, a decision maker named as “trigger” gives a bit pattern which allows the fired detectors identification. As the data acquisition dead time is greater than the time between physical events, timing information is essential. We add to the trigger function a Time to Digital Converter (TDC) in order to make a separation between events. The paper describes the architecture chosen for the TDC and illustrates the contribution of each element to the TDC performance. An eight-bit counter is used for the dynamic range of the TDC (in microsecond) associated to a delay line improving the resolution (in nanosecond). The study shows that exploiting the two system clock states (high and low) allows to reduce the number of delay line cells. The Differential Nonlinearity Measurements are given for different resolutions (1, 2 and 5ns) and illustrate the clock period, the clock duty cycle and the delay line contributions to the TDC performances.