Parallel Implementation Of Computing-Intensive Decoding Algorithms Of H.264 On Reconfigurable Soc

Computing-intensive algorithms which occupy most of executing time are always the main bottleneck in real-time or high quality video applications. In this paper, the optimization methods of the computing-intensive decoding algorithms of H. 264, including MC (Motion Compensation), Deblocking and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization), are proposed firstly, and then implemented on the REMUS (REconfigurable MUltimedia System) which is an embedded coarse-grain reconfigurable multimedia system. Tests show that the efficiency of MC is improved by 32.5%, Deblocking by 69% and IDCT-IQ by 88.5% compared with XPP PACT(a commercial reconfigurable processor). Compared with typical ASIC solutions, execution performance of MC and IDCT improved by 49% and 17%, respectively, while that of Deblocking remained about the same.