A Massively Multithreaded Packet Processor

This paper introduces a new packet processor designed for stateful networking applications: those applications where there is a requirement to support a large amount of state with little locality of access. Stateful applications require a high rate of external memory accesses, and this in turn implies a high degree of parallelism is needed. Our packet processor utilizes multiple multithreaded processing engines to support this parallelism in a design that supports 256 simultaneous threads in eight processing engines. Each thread has its own independent register file and executes instructions formatted to a general purpose ISA, while sharing execution resources and memory ports with other threads. The processor is optimized to sacrifice single threaded performance, so that a design is achieved that is realizable in terms of silicon area and clock frequency. The use of a general purpose ISA and other features achieves a design in which software porting issues are minimized.