Design For Testability Of Functional Cores In High Performance Mode Architectures

Grand challenge applications have been the major source of inspiration for many technological innovations in the field of computing, in particular the node architecture design for supercomputing [1, 2, 3], Since the performance of supercomputers to a large extent is reflected by that of the computing node, it is imperative that the node architecture caters to the demands posed by these massive applications. Research attempts in this direction have proposed that the node architectures be stacked with multiple homogenous cores. However, these efforts do not effectively scale the node performance [7], suggesting a possible performance bottleneck and also raising the issue of performance reliability in such node architectures [5]. In this context, we propose a generalised methodology for design of functional cores consisting of higher order algorithm-level functional units that can be tested online, ensuring both greater performance and reliability. These functional units are realised using arrays of Memory-In-Logic (MIL) cells [3], paving the way for cell-based Iterative Array Architectures. The high performance testable designs of functional units such as the Kernighan-Lin (KL) graph partitioning unit and the matrix multiplication unit have been presented in detail. A novel testing methodology for simultaneous online testing of both memory and logic components for such functional units is also proposed.