Shallow Source/drain Extension Effects on External Resistance in Sub-0.1 /spl Mu/m MOSFETs

Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R-acc) is highly dependent both on the SDE junction depth (X-j) and the gate overlap length (L-ov). Due to the laterally finite doping gradient, R-acc becomes dominant among other external resistance components in sub-0.1 mu m MOSFET's. Hence, device optimization to minimize R-acc is necessary in order to improve on-current and SDE to the gate coupling. A NMOS transistor with L-eff of 0.08 mu m show's a maximum on-current while maintaining a lower off-leakage current for a L-ov of 20 nm and X-j of 40 nm.