Flip Chip Power Mosfet: A New Wafer Scale Packaging Technique

A Arzumanyan,R Sodhi,D Kinzer, H Schofield, T Sammon

ISPSD'01: PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS(2001)

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Abstract
This paper describes the first flip chip power MOSFET device with the lowest R-DSON per footprint area in the industry. This device, with the same electrical characteristics as an SO8 packaged device, takes only 30% of the SO8 footprint. R-Si x Footprint Area as low as 59 mOhm.mm(2) were achieved for bi-directional device and 98 mOhm.mm(2) for single device at 4.5 V-GS, a 4-6 times reduction compared to regular packaged MOSFET. The typical applications for these parts include battery charging and load switching in cell phones and laptops.
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Key words
silicon,power mosfet,metallization,flip chip,chip scale packaging,electrodes,surface resistance
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