Edge-defined self-alignment of submicrometer overlaid devices

S. D. S. Malhi,P. K. Chatterjee, T. D. Bonifield,J. E. Leiss, D. E. Carter,R. F. Pinizzotto,D. J. Coleman

IEEE Electron Device Letters（1984）

Cited 7|Views4

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Abstract

A novel device structure for self-aligning the overlaid device in a stacked CMOS process is introduced and demonstrated. The structure allows submicrometer channel length devices to be fabricated without using advanced lithographic technology. The self-alignment feature should permit a dense layout for CMOS static RAM applications.

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Key words

CMOS process,Random access memory,Boron,Implants,Etching,CMOS technology,SRAM chips,Power dissipation,Read-write memory,MOSFETs

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