Low Power 20-GHz Current-Mode Frequency Divider in 0.18-um CMOS Phase-Locked Loop

This paper proposes a high performance current mode logic (CML) frequency divider for an integrated analog phase-locked loop (PLL). The frequency divider includes the inductive peaking structure with the cascode circuit. In order to obtain a high speed circuit with stable frequency response, the resistor in the inductive peaking structure is replaced by the cascode circuit which is operated by DC bias voltage in MOS gate. The proposed frequency divider is applied to the feedback circuit of an analog PLL with 0.18 碌m CMOS process. Simulation shows that the six stages of 2:1 divider provide the expected frequency characteristics at the input frequency of 20 GHz. The power consumption of the proposed divider is obtained to be 6.9 mW.