A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Jin-Cheol Seo,Sang-Soon Im,Kwan Yoon,Seung-Wook Oh,Taek-Joon An,Gi-Yeol Bae,Jin-Ku Kang

SoCC（2012）

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摘要

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 231-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply.

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关键词

cmos integrated circuits,displayport 1.2 standard,recovered-clock jitter,voltage-controlled oscillators,voltage 1.2 v,size 65 nm,jitter,clock and data recovery circuit,bit rate 5.4 gbit/s,triple data rate,bit rate 1.62 gbit/s,dual-loop architecture,cmos technology,bit rate 2.7 gbit/s,phase locked loops,vco,phase-locked loop,phase detectors,integrated circuit noise,frequency locked loops,triple-mode voltage-controlled oscillator,half-rate phase detector,power 11 mw,clock and data recovery circuits,frequency-locked loop,cdr circuit

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