FPGA implementation of FEC encoder in DVB-S2

This paper analyses the characteristic of BCH codes and LDPC codes in DVB-S2, and proposes an encoding architecture for FPGA implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60. The design method adopts many BlockRAMs to process all the parity bits relating to the same information bit in parallel, thus improve the encoding speed. Synthesis results show that this encoder has a throughput about 49.95 Mb/s, and satisfies the demand of DVB-S2 at the cost of low resource occupation.