Testing The 400mhz Ibm Generation-4 Cmos Chip
ITC '97: Proceedings of the 1997 IEEE International Test Conference（1997）
Abstract
This paper describes the design-for-test framework of the 400MHz CMOS central processor (CF) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and. effective rests; as well as describe the test sets required ro test all portions of the design. This includes built-in self-lest, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns, Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.
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Key words
CMOS digital integrated circuits,IBM computers,built-in self test,computer testing,fault diagnosis,integrated circuit testing,logic design,logic testing,microprocessor chips,random-access storage,400 MHz,CMOS chip,IBM S/390,LBIST,RAM,algorithmic pattern generation,array self-test,design-for-test,failures diagnosis,flush test,modeling,scan test,weighted random pattern,weighted random pattern generation,
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