Generating Telecommunication Architectures in the DSP Station Environment

The C Telecommunication library within DSP Station CAD framework is provided on ly for simulation pu rpose. These Telecom C primitives do on ly exec ute the c orresponding a lgorithms without any hardware implementation concepts. Consequently, the designer is confronted to a dead end when trying to generate the final synthesisable telecom design from his (or her) C telecom processor description. The GENCELL project (EUREKA project in collaboration with Mentor Graphics) aims to p ropose a no vel design flow and its s upporting tool t o o vercome this important restriction. Our design flow starts from high level requirements and constraints s uch a s implementation style, da ta size, error r ecovering, information to the final synthesisable VHDL telecom architecture. These constraints are derived from the simulation results and from the parameters of the C units selected from the telecom design library. This method is mainly based on a repository of highly flexible and synthesisable VHDL cells dedicated to telecom applications and a configurable expert library management system. The Module Manager is an expert system able to select t he most appropriate telecom cells according to the designer's r equirements and to p rovide all t he necessary information to d rive the Mistral2 synthesis process in o rder to g enerate our s pecific low-power target architecture. A first application implements a telecommunication transmitter including source and channel encoders as well as framing devices.