A DLL with Jitter-Reduction Techniques for DRAM Interfaces.
ISSCC（2007）
Key words
CMOS integrated circuits,DRAM chips,delay lines,delay lock loops,jitter,0.13 micron,1 GHz,CMOS process,DLL,DRAM interfaces,delay-locked loop,jitter-reduction techniques,noisy environment,replica delay line,supply noise
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