Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications

In this paper, we describe our triple sidewall spacer scheme to achieve 45 nm ground rule for high-performance applications. This triple sidewall spacer scheme uses three kinds of sidewall spacers, in which the first sidewall is used for the source/drain extension implantation offset (SW1), the second is for the p-channel field effect transistor (PFET) embedded silicon germanium offset (SW2), and the third spacer is for the deep source/drain implantation offset (SW3). We also evaluated the impact of sidewall spacer materials and structures on device characteristics. After optimizing each sidewall spacer material and structure including offset width, we successfully demonstrated identical device characteristics with the minimum poly-pitch layout while minimizing layout dependence. This sidewall spacer scheme has the capability to achieve the 45 nm ground rule, and our sidewall spacer design is mature and suitable for 45-nm-node high-performance applications. (C) 2009 The Japan Society of Applied Physics