2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

Dinesh Somasekhar,Yibin Ye,Paolo Aseron,Shih-Lien Lu,Muhammad M. Khellah,Jason Howard,Greg Ruhl,Tanay Karnik,Shekhar Borkar,Vivek K. De,Ali Keshavarzi

Solid-State Circuits, IEEE Journal of（2009）

引用 96|浏览150

暂无评分

摘要

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.

查看译文

关键词

DRAM chips,logic design,logic devices,pipeline processing,2T gain cell memory macro,byte rate 128 GByte/s,eDRAM cells,frequency 2 MHz,ground precharge bitline,logic process technology,non-destructive read-out,partial write support,pipelined architecture,size 65 nm,2T cell,3T cell,Bandwidth,dram,eDRAM,gain cell,memory

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要