Investigation of N-Channel Triple-Gate Metal-Oxide-Semiconductor Field-Effect Transistors on (100) Silicon On Insulator Substrate

We have investigated the fabrication processes and device characteristics for n-channel triple-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) on (100) silicon-on-insulator substrates. By optimizing the diagonal ion implantation conditions for the narrow fin channel, the fabricated triple-gate device showed an electron mobility almost compatible to a planar MOSFET with a supreme subthreshold slope of 64 mV/decade and drain induced barrier lowering (DIBL) of 15 mV/V.