Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory
DAC(2014)
摘要
SRAM based register file (RF) is one of the major factors limiting the scaling of GPGPU. In this work, we propose to use the emerging nonvolatile domain-wall-shift-write based racetrack memory (DWSW-RM) to implement a power-efficient GPGPU RF, of which the power consumption is substantially reduced. A holistic technology set is developed to minimize the high access cost of DWSW-RW caused by the sequential access mechanism. Experiment results show that our proposed techniques can improve the GPGPU performance by 4.6% compared to the baseline with SRAM based RF. The RF energy efficiency is also significantly improved by 2.45×.
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关键词
sram based register file,racetrack memory,sram chips,register file,gpgpu register file architecture,graphics processing units,sequential access mechanism,dwsw-rm,domain-wall,gpgpu,nonvolatile domain-wall-shift-write based race-track memory,rf energy efficiency,holistic technology set,multiple data stream architectures,domain wall
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