Esd Protection Circuit With Low Triggering Voltage And Fast Turn-On Using Substrate-Triggered Technique

In this paper, ESD protection circuit with substrate-triggered technique using PNP bipolar transistor for quick discharge of the electrostatic energy is proposed. The proposed ESD protection circuit is verified by the transmission line pulse (TLP) system. The results show that the proposed ESD protection circuit has lower trigger voltage (5.98 V) compared with that of conventional GGNMOS. And the proposed circuit has faster turn-on time (similar to 37 ns) than that of the conventional substrate-triggered ESD protection circuit.