A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

IEEE Journal of Solid-State Circuits(2007)

引用 37|浏览41
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摘要
Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog dela...
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关键词
Graphics,SDRAM,Clocks,Circuits,Random access memory,Timing,Frequency,Delay,Jitter,Noise reduction
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