Refining Power Consumption Estimations In The Component Based Aadl Design Flow

FDL(2008)

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摘要
This paper presents a method that permits to quickly estimate the power consumption at the first steps of a system's design. We present multi-level power models and show how to use them at different levels of the specification refinement in the component based AADL design flow. PET, a power estimation tool, is being developed in the frame of the European SPICES project. It first prototype gives, in the case of a processor binding, power consumption estimations, for software components in the AADL component assembly model, with a maximal error ranging roughly from 5% to 30% depending on the refinement level. We illustrate our approach with the power model of the PowerPC 405, and its use at different levels in the AADL How.
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关键词
SPICE,embedded systems,power consumption,simulation languages,European SPICES project,architecture analysis,architecture design language,modelling language,power consumption estimations,power estimation tool,processor binding,real-time embedded systems,software components,specification refinement
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