Automatic Soc Design Flow On Many-Core Processors: A Software Hardware Co-Design Approach For Fpgas

Traditional FPGA-based system-on-chip (SoC) design in general is accomplished via separate software and hardware design flows. With such a separate design methodology, extra development overhead has to be paid to meet the final system's performance, size and power consumption requirements. To overcome this development overhead which usually leads to significant increase of the time-to-market, a unified and efficient SoC design flow is needed. The current work addresses this problem via a SoC design flow which allows automatic building of a complete autonomous system on an FPGA in accordance with the need of a specific application. In the proposed design flow the architecture of the generated hardware is tailored to match the parallelism granularity and communication structure of the application. This, in turn, allows the application developer to meet the system's performance, size and power consumption requirements with a short time-to-market. To prove the applicability of the proposed approach, a monitor for real-time electrocardiographic (ECG) signal analysis and a motion detection algorithm have been implemented.