MuCCRA-3: a low power dynamically reconfigurable processor array

Yoshiki Saito,Toru Sano,Masaru Kato,Vasutan Tunbunheng,Yoshihiro Yasuda,Masayuki Kimura,Hideharu Amano

ASP-DAC（2010）

Cited 13|Views13

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Abstract

MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC (System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. DRPAs including MuCCRA-3 provide multiple sets of configuration data called hardware contexts, and switch them in a clock cycle.

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Key words

CMOS integrated circuits,system-on-chip,ALU,MuCCRA-3,dynamic reconfiguration,flexible off-loading engine,low power CMOS process,low power dynamically reconfigurable processor array,processing elements,register file,simple coarse-grained processor,system-on-a-chip,time-multiplexed execution

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