Test clock domain optimization for peak power supply noise reduction during scan

Jen-Yang Wen,Yu-Chuan Huang,Min-Hong Tsai,Kuan-Yu Liao,James Chien-Mo Li,Ming-Tung Chang,Min-Hsiu Tsai,Chih-Mou Tseng,Hung-Chun Li

ITC（2011）

引用 2|浏览12

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摘要

This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.

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关键词

test clock domain optimization,half million gate design,benchmark circuits,circuit noise,power supply circuits,circuit optimisation,maximum flip-flop density,design for testability technique,clocks,peak power supply noise reduction,partition technique,ir drop simulation tool,dft technique,scan chain shifting,time 3 hour,flip-flops,design for testability,circuit testing,time 14 min,optimization,automatic test pattern generation,benchmark testing,logic gate,logic gates,noise reduction

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