Extensible open-source framework for translating RTL VHDL IP cores to SystemC
DDECS(2013)
Abstract
SystemC has gained wide acceptance in the design of VLSI SoCs. At the same time there exists a large number of legacy IP cores described in VHDL whose reuse and integration into SystemC ecosystem is highly demanded. However, there is a lack of any standard approach in this regard. This paper proposes an open-source framework and methodology to convert RTL VHDL IP cores to cycle-accurate SystemC designs. The SystemC output is emphasized to be human-readable and providing for clear correspondence to the source VHDL code, thus allowing further manual code changes and debug. The described framework has been implemented based on an open-source zamiaCAD platform and has been successfully applied to translate various VHDL benchmark designs.
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Key words
systemc,rtl,cycle-accurate systemc designs,manual code debug,rtl vhdl ip cores,systemc ecosystem,vlsi soc design,system-on-chip,manual code changes,vhdl,vlsi,integrated circuit design,vhdl benchmark designs,extensible open-source framework,open-source zamiacad platform,legacy ip cores,source vhdl code,benchmark testing,sensitivity,hardware,system on chip
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