Rtl Controller Synthesis

RTL synthesis from Verilog or VHDL involves many tradeoffs between controller and data path synthesis. Many advanced modeling constructs and design styles require a sophisticated controller implementation. Important design decisions include the choice between implicit/explicit finite state machines (FSMs), the choice of active control and data edges in a synchronous design, the determination of control inputs/outputs, the proper modeling of an asynchronous or synchronous reset signal and, in Verilog, the usage of advanced modeling constructs such as named events, waits and disable statements in an efficient manner. We present our interpretation of the issues in an RTL synthesis system, based on the principles that the synthesized result must match simulation under 'all conditions, and that the interpretation must be efficient for both simulation and synthesis. The primary difficulty is to produce a synchronous implementation of the advanced (asynchronous) modeling constructs.