Advanced wafer thinning technology and feasibility test for 3D integration

The ultra-thinning less than 0.5@mm of total thickness variation (TTV) within 300mm wafer has been developed for the wafer-on-a-wafer (WOW) application. TTV was controlled by measuring wafer thickness and parallelity between grinder and wafer surface, called Auto-TTV method. Surface treatment to remove damage layer such as defects and non-crystalline layer was also developed. For the ultra-thinning less than 10@mm in wafer thickness, no significant device degradation in the high performance 45nm node CMOS and FRAM memory was revealed. The impact of ultra-thinning processes on strained transistors and Cu/low-k multilevel interconnects as well as FRAM memory is described. Properties examined include stack chain resistance of Cu@a interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors for CMOS logic, and switching characteristics for FRAM before and after thinning. It was found that the electrical properties were not affected by bonding, thinning and debonding process, indicating good feasibility of 3D stacking integration.