Meeting real-time requirements with multi-core processors

Many multi-core processors exhibit characteristics that make it difficult or even impossible to use them in safety-critical real-time systems. To prevent sporadic failures and late-stage integration problems, the hardware properties of the processor and its peripherals have to be checked for their real-time capability at an early project stage. Selecting a configuration which enables predictable performance is an important requirement to achieve compliance with current safety standards, e.g., ISO-26262, IEC-61508, EN-50128, or DO-178B. For timing-predictable hardware configurations safe worst-case execution time bounds can be computed by static analysis tools. Combined with scheduling analysis at the system level the correct end-to-end timing can be guaranteed. This article gives an overview of hardware features leading to predictability problems, shows examples of predictability-oriented multi-core configurations, and describes a tool-based methodology to ensure the correct timing behavior.