A Novel HW/SW Partitioning with SIMD Instructions for AVS Video Decoder

In this paper, we propose a novel HW/SW partitioning with SIMD instructions for the real-time AVS video decoder. As the SIMD instructions instead of hardware are used to optimize video decoding, our approach achieves an optimal balance between performance and programmability. We implement the proposed HW/SW partitioning on a 32-bit RISC processor with 256-bit vector extension, and evaluate the performance using some standard high-quality streams of AVS. Results show that the video decoding system can support the real-time decoding of AVS HD video streams.