An Embedded SRAM IP Compiler Design Methodology Independent of Technology and Circuit Structure
ICETCE '12 Proceedings of the 2012 Second International Conference on Electric Technology and Civil Engineering（2012）
Abstract
This paper presents a novel SRAM IP compiler design methodology that greatly decreases compiler design time and complexity. When designing a new compiler, designers only need to update algorithm written in high level functions and leave rest work to specialized tools which are developed to handle foundry, technology or certain circuit structure relevant information. A new compiler verification approach based on statistics and a Synopsys technology library generating approach based on simulation and interpolation are also discussed in this paper.
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Key words
compiler design time,new compiler,new compiler verification approach,novel SRAM IP compiler,Synopsys technology library generating,design methodology,certain circuit structure,high level function,relevant information,rest work,Circuit Structure,Methodology Independent,SRAM IP Compiler Design
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