Performance analysis of FPGA interconnect fabric for ultra-low power applications

Fabrication cost of ASICs is increases rapidly for deep submicron technology. It is important to explore the different techniques to reduce the FPGA power consumption so that in future they can also be deploy in place of ASICs in portable energy constrained applications. Since power is an important design constrain for FPGA in nanometer technology, it is important to investigate the possibility of extending the use of FPGA to the subthreshold region for ultra low power applications. Interconnect fabric of an FPGA consumes a large amount of the chip power, area and determines the overall circuit delay. Exponential increase in resistance of interconnects driver in subthreshold region gives huge penalty in terms of speed of FPGA interconnect fabric. Improving speed is one of the subthreshold circuit design challenge. In particular, this paper investigates the performance of FPGA interconnect resource using CMOS, Carbon Nano Tube Transistors (CNFETs), FinFET and operating drivers in near threshold region. The proposed interconnect fabric in which drivers are operated in near threshold voltage shows 3.6 X, 3X and 1.25X improvement in speed over conv. CMOS, Opt-CNFET and FINFET driver based HEX interconnect resource.